The continuing trend in the semiconductor industry toward densification of circuit devices has significantly improved performance of electronic devices that use integrated circuits. In a typical integrated circuit, individual circuit elements are electrically connected together by a metallization process in which layers of metal are deposited and patterned to form metal lines that complete the circuit as designed. Multiple metal layers are often employed. Metal lines within patterned metal layers are insulated by interlevel dielectric layers from undesired electrical contact both with other metal lines, whether in the same or another metal layer, and with other circuit elements.
In the construction of integrated circuit structures, dielectric materials such as silicon oxide (SiO2) have been conventionally used to electrically separate conductive elements of the integrated circuit structure. The increasing density of integrated circuits has resulted in unneeded capacitance between metal lines in an integrated circuit which slows circuit speed and can cause cross-coupling between adjacent conductive elements.
The use of insulation materials having lower dielectric constants (k values) than conventional silicon oxide (SiO2) have been described. One such class of material is a carbon doped silicon oxide material wherein at least a portion of the oxygen atoms bonded to the silicon atoms are replaced by one or more organic groups, for example, an alkyl group such as a methyl (CH3) group. Such low k carbon doped silicon oxide dielectric materials have dielectric constants varying from about 2.5 to about 3.5, and lowers the capacitance between conductive elements separated by such dielectric materials.
In connecting overlying layers of metal lines separated by a carbon-doped SiO2 interlayer dielectric (ILD) layer, a photolithographic technique is used that typically employs a dielectric antireflective coating (DARC) layer and an overlying photoresist layer. High aspect ratio features such as vias/trenches that are etched through the ILD layer to an underlying metal line are subsequently cleaned to remove post-etch polymer and the DARC layer before depositing the metal fill. Current cleaning compositions etch a portion of the ILD layer during the cleaning step, which can have a negative impact on and significantly alter the critical dimensions of the etched feature.
Therefore, a need exists for a cleaning composition and process that overcomes such problems.